With the scaling of metal oxide semiconductor field effect transistors (MOSFET), MOSFETs physical dimensions have been reduced to maintain dimensional similitude and reliability. MOSFET constant electric field scaling theory requires the physical scaling of dimensions to maintain a constant reliability of the MOSFET gate dielectric. To maintain scaling of the transistor, the three-dimensional FinFET was introduced in advanced technology nodes.
FinFET structures have been proposed for both bulk CMOS and silicon on insulator (SOI) technology. In these advanced technology nodes, reliability is a concern in the FinFET devices. Reliability concerns in FinFETs include hot electron, drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL), latchup, electrostatic discharge (ESD), electrical overstress (EOS), electromigration (EM), and detrimental effects associated with radiation. Radiation effects can include total dose gamma radiation degradation, total ionizing dose (TID), single event upsets (SEU), single event latchup (SEL), and single event gate rupture (SEGR). These reliability issues that occur in CMOS MOSFETs also occur in FinFET structures.
Radiation effects can occur from both radioactivity of naturally occurring materials used in semiconductors. Alpha particles are generated from the radioactive decay from uranium and thorium isotopes in materials used in semiconductor electronics (e.g. aluminum, silicon, lead). Cosmic rays create single event failures in both space and terrestrial environments. Cosmic rays include neutrons, protons, and muons. Neutrons can interact with the boron atoms used in borophosphosilicate glass (BPSG) back end of line (BEOL) materials. Cosmic rays introduce silicon recoil events, and silicon fission in the semiconductor substrate, leading to ionizing tracks. Ionizing tracks generate electron hole pair generation influencing FinFET devices. Heavy ions in space environments can lead to single event latchup (SEL). Ionizing radiation occurs naturally in the form of high-energy photons or charged particles that possess enough energy to break atomic bonds and create electron hole pairs in an absorbing material. These particles can include protons, electrons, atomic ions, and photons with energies greater than a bandgap of the absorbing material. When typical integrated circuits, such as FinFET integrated circuits, are exposed to the charged particles over a period of months or even years, the ionizing radiation can contribute to a total ionizing dose (TID). For example, as an ionizing particle passes through a FinFET device, it generates one or more electron-hole pairs which can be trapped in the gate oxides and the field oxides. Electrons in the semiconductor's valence band are raised to the conduction band. A fraction of the electron-hole pairs will undergo initial recombination and cause no damage, but such recombination decreases as the electric field increases, and the electrons and holes that survive it are free to diffuse and drift within the oxide where they will be swept from the insulator, recombine, or be trapped.
FinFET structures in bulk CMOS have small channel regions where self-heating occurs in the channel region. The physical separation from the silicon substrate prevents thermal transfer of the Joule heating to the bulk substrate. The region between the FinFET channel and the substrate adds thermal resistance leading to self-heating of the FinFET structures. The self-heating of the FinFET structure can lead to reliability concerns in the semiconductor chip.
FIG. 1 illustrates a prior art FinFET structure 100 formed on a lightly-doped p-type substrate 101. A fin structure 113 includes a fin body 104 disposed on and extending above the upper surface 114 of the substrate 101. An isolation structure 102 is formed below the upper surface 114 of the substrate 101, and includes respective isolation regions 102A, 102B disposed on opposite sides of the fin body 104. The isolation structure 102 is also known as shallow trench isolation (STI), which is typically planar with the silicon surface in a planar MOSFET technology. A fin connecting region 103 is disposed in the substrate 101 below the fin body 104 and between the isolation regions 102A, 102B. A gate dielectric layer 105 is disposed on three sides of the fin body 104, and a gate electrode 106 is disposed on the gate dielectric layer 105 (i.e., wrapping around three sides of the fin body 104). A P+ substrate contact 107 provides contact to a well region 112 underlying the isolation structure 102 and the fin structure 113. The substrate contact 107 is formed through the isolation structure 102, which is shown in this cross-sectional view as passing through adjoining isolation regions 102. In the case of an n-channel FinFET, the substrate contact and the well region is p-type. In the case of a p-channel FinFET structure, the well region 112 and substrate contact 107 are n-type. Frequently both an n-type FinFET and a p-type FinFET structure are integrated on the same substrate. Each type is placed in the respective well and contact structures. A FinFET may be constructed in a technology without a well region, or with a single well (e.g., n-well), or with a dual well (e.g., n-well and p-well), or with a triple well (e.g., a p− epi region isolated from the p-substrate by a n+ region). The presence of the isolation structure 102 increases the thermal resistance of the FinFET structure, leading to self-heating in the FinFET fin body 104. The isolation regions 102A, 102B may be tapered (as shown at edge 115) to provide lower electrical and thermal series resistance from the fin connecting region 103 to the underlying substrate 101. Increased taper angle of the isolation regions 102A, 102B increases the spacing between two adjacent fin 113 structures (i.e., fin-to-fin spacing). With the trend to lower-doped substrate wafers, both the electrical resistance and the thermal resistance increase with each technology generation.
FIG. 2 illustrates a prior art FinFET structure 200 formed on a silicon on insulator (SOI) substrate 201. A fin structure 213 includes a fin body 204 disposed on and extending above the upper surface 214 of the substrate 201. An isolation structure 202 is formed below the upper surface 214 of the substrate 201, and includes respective isolation regions 202A, 202B disposed on opposite sides of the fin body 204. A fin connecting region 203 is disposed in the substrate 201 below the fin body 204 and between the isolation regions 202A, 202B. The fin connecting region 203 extends vertically from the upper surface 214 of the substrate 201 to the bottom surface 216 of the isolation structure 202. The fin body 204 is the active region of the FinFET device and is surrounded on three sides by a gate dielectric layer 205 disposed on the fin body 204. A gate electrode 206 is disposed on the gate dielectric layer 205, wrapping around three sides of the fin body 204. A P+ substrate contact region 215 is formed through the isolation structure 202 and provides contact to a well region 209 underlying the isolation structure 202 and the fin structure 213. The presence of the isolation structure 202 increases the thermal resistance of the fin connecting region 203, and leads to increased self-heating in the FinFET fin body 104. Tapering the isolation regions 202A, 202B (and thus tapering the fin connecting region 203) lowers the thermal resistance, but negatively impacts the spacing of adjacent FinFET fingers (e.g. fin-to-fin spacing), leading to a lower circuit density. A buried oxide (BOX) layer 207 is formed in the substrate 201. A substrate contact 208 penetrates through an opening in the isolation structure 202 and extends downward through the well layer 209 and through the buried oxide layer 207 to reach the underlying substrate 201. The substrate contact 208 may utilize a doped polysilicon pillar formed in a trench. The well region 209 disposed at a depth between the isolation structure 202 and the buried oxide layer 207 may contain appropriate dopants forming a single well, a dual well, or a triple well structure. The substrate contact 208 may be electrically isolated from the region 209 by an isolating edge (e.g. dielectric isolation) or an ohmic contact to region 209.
FinFET structures formed in silicon on insulator (SOI) substrate have a buried oxide region 207, further separating the FinFET device active channel region from the silicon substrate. The thermal resistance from the FinFET to the bulk substrate is significantly increased because of the buried oxide structure. The self-heating is a function of the thickness of the buried oxide region. With a thick buried oxide region, the fin body temperature can increase due to self-heating from ambient temperature (e.g. T=300 K) to T=400 K. This can be detrimental to the reliability of the SOI FinFET structure. With the thermal resistance of the fin connecting region 203, the buried oxide layer 207, and the substrate 201, self-heating is a significant concern for 25 nm, 14 nm, 7 nm and 3 nm FinFET devices. Lower doped substrate wafers increases the thermal resistance to the contact structures to remove the Joule heating power generated in the FinFET structure.
CMOS latchup can also occur between a P-type FinFET, and an N-type FinFET. Parasitic bipolar transistors exist in CMOS associated with the parasitic device between the p-type FinFET diffusions, and the n-type FinFET diffusions. Isolation structures help reduce the lateral bipolar current gain between FinFET structures lowering the lateral bipolar current gain. With the tapering of the edges of the isolation, the CMOS latchup immunity is degraded. Hence, to reduce the thermal resistance in the connecting region, the self-heating is lowered, but this degrades the latchup immunity. Initiation of CMOS latchup can occur from electrical overshoot, or single events. Latch-up generally, and in the case of circuits in radiation environments SEL, is a serious failure mode in CMOS circuits. In the best case, latch-up results in soft failure with a loss of data or logic state. In the worst case, latch-up causes a destructive hard failure with permanent loss of the circuit. Thus, from a circuit reliability perspective, latch-up is to be avoided at all costs. As isolation widths shrink, device structures become even more susceptible to both latch-up failure modes.
As noted above, radiation environments present special problems to CMOS circuits in that high-energy particles form electron-hole pairs (EHP) generation in silicon and in the bulk substrate. The instantaneous generation of electron hole pairs deposited by a high-energy particle passing through an IC can immediately induce large displacement currents on the pico-second time scale accompanied with rapid potential shifts away from initial logic states. The deposition of energy by the particle typically causes diodes to forward bias, followed by large transient injection currents which reinforce the transient upset and can cause the CMOS circuit to latch-up.
Additionally, with the widening of the connecting region, more electron-hole pairs (EHPs) are collected in the connecting region of the FinFET, increasing the sensitivity of FinFETs to radiation events.
FinFET sensitivity to transient responses is key in future technology generations. These can include noise, ESD, EOS, and EMC events. Additionally, it is critical for single event upset (SEU) prevention that the circuitry is responsive to transient events to avoid change of circuitry logic states.
Further improvements in FinFET structures for bulk CMOS and for silicon on insulator (SOI) are desired.